Modeling Analog Circuitry with Vhdl

by Mark Dean Mueller With the increasing use of mixed signal analog and digital technologies in circuit design, there becomes a growing need for a method to simulate such circuits quickly, easily and accurately. Modeling the components structurally with an analog simulation tool is a common technique. A more powerful method would be to behaviorally model both types of components at a higher level. The VHSIC Hardware Description Language (VHDL) includes a REAL data type that allows continuous quantities to be represented in its models. Modeling analog components in VHDL is done by determining a constant lumped-parameter transfer function for each component and using REAL data types as signals. Euler's method can then be used to approximate the value of a quantity after a discrete time step. The analog portion of a mixed signal circuit modeled in VHDL can be connected to digital instances much as any other VHDL component.